1. Field of the Invention
The technology relates to memory integrated circuits, in particular the erase operation of a nonvolatile memory integrated circuit.
2. Description of Related Art
Improvement of the over-erase effect from the erase operation has become an increasingly serious problem. Because of higher and higher memory array density, the floating gate coupling effect becomes even more serious.
However, present approaches of the erase operation of nonvolatile memory cells are inefficient. For example, in the erase operation of FIGS. 1-7 over-erased memory cells can result. In another example, such as US Patent Application Publication 2008/0175069, erase verify errors result in indiscriminate subdivision of an erase sector into two groups, followed by further subdivision into further groups, which results in a relatively complicated erase operation. In another example, the excessive use of dummy word lines (WLs) and dummy memory cells in U.S. Pat. No. 7,417,895 is wasteful of potentially usable memory cells.